An inverter is configured to convert direct current power into alternating current power. Circuits of the inverter mainly include an inverter bridge, a control logic circuit, and a filter circuit.
Referring to FIG. 1, a schematic diagram of a main circuit of a typical diode neutral-point-clamped three-level inverter is shown. The main circuit mainly includes four switching tubes, namely, a first switching tube Q1, a second switching tube Q2, a third switching tube Q3, and a fourth switching tube Q4, as well as diodes D5 and D6. Besides, at two ends of each switching tube, a diode is connected in antiparallel with the switching tube, such as diodes D1, D2, D3, and D4 shown in FIG. 1. On and off states of the four switching tubes are respectively controlled through four paths of drive signals. The switching tubes Q1 and Q4 are outside a bridge arm and are called outer tubes (hereinafter referred to as outer tubes); Q2 and Q3 are inside the bridge arm and are called inner tubes (hereinafter referred to as inner tubes).
Specifically, when an output voltage of the diode neutral-point-clamped three-level inverter is in a positive half cycle, the switching tube Q2 is normally turned on, the switching tube Q4 is normally turned off, the switching tubes Q1 and Q3 are turned on in a complementary manner and dead time is ensured; when the output voltage of the diode neutral-point-clamped three-level inverter is in a negative half cycle, the switching tube Q3 is normally turned on, the switching tube Q1 is normally turned off, the switching tubes Q2 and Q4 are turned on in a complementary manner and dead time is ensured. The dead time is a protection time period set to ensure that switching tubes above and under a bridge arm are not simultaneously turned on due to a problem of turn on/off delay in the switching tubes during a process of controlling the switching tubes in a bridge circuit.
Referring to FIG. 2, a schematic diagram of a control logic circuit in the circuit shown in FIG. 1 is shown. The control logic circuit mainly includes a first controller 1, a second controller 2, an inverter current detecting circuit 3, and an overcurrent occurrence detecting circuit 4. Basic control strategies are as follows: the first controller 1 generates two paths of SPWM (Sinusoidal Pulse Width Modulation, sinusoidal pulse width modulation) drive pulses that include a dead time, namely, PWM1 and PWM2, as well as an output voltage positive/negative half cycle enabling signal EN. When the EN is at a low level, an output voltage of the three-level inverter is in a positive half cycle. When the EN is at a high level, the output voltage of the three-level inverter is in a negative half cycle. According to the three-level inverter logic and by using the PWM1, PWM2, the second controller 2 generates four paths of drive pulses, which are Q1PWM, Q2PWM, Q3PWM, and Q4PWM and respectively drive the switching tubes Q1, Q2, Q3, and Q4.
The inverter current detecting circuit 3 detects a current that flows through the switching tubes in real time and sends a detected inverter current signal Iinv to the overcurrent occurrence detecting circuit 4. When the detected inverter current has a value greater than a preset current value, the overcurrent occurrence detecting circuit generates an overcurrent signal OC and provides the signal to the second controller 2. The second controller 2 blocks drive pulses of all switching tubes in an inverter 5 to turn off all the switching tubes. When the overcurrent disappears, the overcurrent signal OC output by the overcurrent occurrence detecting circuit 4 is flipped, so that the second controller 2 generates normal drive pulses to restore the switching tubes in the inverter to normal on/off states.
Referring to FIG. 3, a schematic diagram of drive pulse waveforms in a current limiting solution in the prior art is shown. As shown in FIG. 3, when an overcurrent signal OC is at a high level, which indicates that an inverter current has a value greater than a preset current value, a current-limiting state is entered. When the overcurrent signal OC is at a low level, which indicates that the inverter current has a value smaller than the preset current value, the current-limiting state is exited.
As shown in FIG. 3, at the time point t1, the overcurrent signal OC is flipped and the current limiting logic is executed. Time is delayed until the time point t2, after it is confirmed that the overcurrent signal OC is not an interference signal and is flipped, the outer tubes Q1 and Q4 are turned off; time is delayed until the time point t3, the inner tubes Q2 and Q3 are turned off; at the time point t4, the overcurrent signal OC is flipped, and the inner tubes Q2 and Q3 are turned on at the same time; time is delayed until the time point t5, if the output voltage is in a positive half cycle, Q3 is turned off; if the output voltage is in a negative half cycle, Q2 is turned off; time is delayed until the time point t6, the drive logic of the four tubes is restored at the same time. When the current-limiting state is exited, the two inside switching tubes (hereinafter referred to as inner tubes for short) Q2 and Q3 are changed from the off state to the on state at the same time. At this time, the outside switching tube (hereinafter referred to as outer tube for short) Q1 or Q4 bears single bus voltage plus an additional voltage generated by a line parasitic parameter, which easily causes relatively high voltage stress on the outer tube and further causes an outer tube failure.